Design Switched Capacitor Filter Sub Circuit Using Tanner EDA Tool

Switched Capacitor circuits are Pervasive in highly integrated, mixed signal Applications. Switched capacitor circuits fill a Critical role in analog/digital interfaces particularly highly integrated applications. This Chapter describes the basic building blocks that Comprise switched Capacitor circuits. These Blocks are the sample-and-hold (S/H), gain Stage. From these elements more complex Circuits can be built such as filters, analog-toDigital converters (ADC) and digital-toanalog Converters (DAC). All sampled-data circuits, Such as these, require a pre-conditioning, Continuous-time; anti-alias filters to avoid Aliasing distortion. 1. Sample-and-hold (S/H) The sample-and-hold is the most basic and ubiquitous switched-capacitor building block. Before a signal is processed by a discrete-time system, it must be sampled and stored. This often greatly relaxes the bandwidth requirements of following circuitry which now can work with a DC voltage. Because the S/H is often the first block in the signal processing chain, the accuracy and speed of entire application cannot exceed that of the S/H. 1.1 Top-plate S/H In CMOS technology, the simplest S/H consists of a MOS switch and a capacitor as shown in figure 1.1. When Vg is high the NMOS transistor acts like a linear resistor, allowing the output Vo to track the input signal Vi. When Vg transitions low, the transistor cuts off isolating the input from the output, and the signal is held on the capacitor at Vo. Srinivasan G & Dr. Murugappan S 272 Figure 1.1: MOS sample-and-hold circuit. There are several practical limitations to this circuit. Because the RC network has finite bandwidth, the output cannot instantaneously track the input when the switch is enabled. Therefore, a short acquisition period must be allocated for this (exponentially decaying) step response. After the S/H has acquired the signal, there will be a tracking error due to the non-zero phase lag and attenuation of the sampling network. The latter linear, low-pass filtering does not introduce distortion and is usually benign for most applications. The on-conductance, however, of the transistor is signal dependent: ID = u Cox W/L (Vg -Vi -Vt) (1.1) Thus the transfer function from input to output can become significantly nonlinear if (Vg Vi Vt) is not sufficiently large. When the switch turns off, clock feed-through and charge injection introduces error in the output. When the gate signal Vg transitions from high to low, this step AC couples to the output Vo via parasitic capacitances, such as Cgs and Cgd. Because the output is a high impedance node, there is no way to restore the DC level. This coupling is called clock feed-through. This error is usually not a performance limitation because it is signal-independent and therefore only introduces an offset and not distortion. To first order this error can be eliminated using a differential configuration. Charge injection, however, is a signal-dependent error. When switch is turned off quickly, the charge in the channel of the transistor is forced into the drain and source, resulting in an error voltage. The charge in the channel is approximately given by equation 1.2 because q is signal dependent; it represents a gain error in the S/H output. There have been several efforts do accurately characterize this error. q = WL Cox (Vg Vi Vt) (1.2) This circuit is also sensitive to parasitic capacitance. Any parasitic capacitance at the output change the amount of signal charge sampled, which is often the critical Node Density Related Index Based Energy Efficient Technique for Congestion 273 quantity in switched-capacitor circuits. Bottom-plate sampling can greatly reduce these errors. 1.2 Gain stage Figure 1.2 shows a gain stage that samples the input, applies gain, and holds the output value. A single-ended version is shown for simplicity, but the following analysis applies to a differential version which is most commonly used in practice. Fig. 1.2: Single ended gain stage To better understand the operation of this circuit, figures 1.3(a) and 1.3(b) show the states of the switches during phase 1 and phase 2 respectively. During phase 1 (figure 1.3a), the input Vi is sampled across Cs. The op-amp is not used during this phase, and this time can be used to perform auxiliary tasks such as resetting common-mode feedback Figure 1.3 (a): Phase 1 Figure 1.3(b): Phase 2 The charge q is: q =Cs (0 Vi) = -Cs Vi (1.3) Notice there is no charge stored on Cf since both sides are grounded. Bottom plate sampling is employed, and the sampling instant is defined by Φ' as before. During phase 2 (figure 1.3b), the op-amp is put in a negative feedback configuration, forcing node x to zero (virtual ground). Because the input is also ground, there is no charge storage on Cs, and all the charge is transferred to Cf. Thus, a voltage gain of Cs/Cf is achieved. Analytically, charge on node x is conserved,